About the Clock Control Register
AMD Top Secret
Public Machine-Specific Registers
Undocumented Machine-Specific Registers
About the Clock Control Register
Theoretical determination of the Clock Ratio locking
Thermal and electrical specification of the AMD64 CPU's
Thermal and electrical specification of the 7th Gen. CPU's

This table shows how the CLK_Ctl*Register controls the Halt
State and Stop-Grant State while system bus is disconnected.

Updated: 01/26/2004




Halt disconnect divisor

Stop-Grand disconnect divisor

Icc(Current)in the SG State

mobile AMD Athlon 4 0662h 60079263h 128 512 0.80-2.00 A
mobile AMD Duron 0671h 60079263h128512 0.80-2.00 A
AMD Athlon XP-M06A0h 20071263h 128128
AMD Athlon XP 0662h 6003D22Fh 64 64 0.66-1.54 A
AMD Athlon XP 0680h 60031223h 8 8 3.70-8.85 A
AMD Athlon XP 0681h 20031223h 8 8 4.90-8.90 A
AMD Athlon XP 06A0h 20031223h 8 8 7.20-12.1 A
AMD Athlon MP 0662h 6003D22Fh 64 64 0.61-2.69 A
AMD Athlon MP 0680h 6003D22Fh 64 64 4.70-8.85 A
AMD Athlon MP 0681h 2003D22Fh 64 64 5.40-8.90 A
AMD Athlon MP 06A0h 2003D22Fh 64 64 6.88-8.75 A
AMD Athlon 064xh FFF0D22Fh 64 64
AMD Duron 063xh FFF0D22Fh 64 64 VCore 1.30V
AMD Duron 0671h 6003D22Fh 64 64 0.66-1.54 A
AMD Duron 0680h 60031223h 8 8 3.90-5.40 A
AMD Duron 0681h 20031223h 8 8 3.90-5.40 A

* BIOS initializes the CLK_Ctl MSR during the POST routine. The CLK_Ctl Register is used to select a halt disconnect divisor and Stop-Grand disconnect divisor for the power states.

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